Semiconductor integrated circuit device

ABSTRACT

Provided is a semiconductor integrated circuit device, which includes: a low-voltage MOS transistor having a source/drain region formed of a low impurity concentration region and a high impurity concentration region; and a high-voltage MOS transistor similarly having a source/drain region formed of a low impurity concentration region and a high impurity concentration region, in which, the source/drain high impurity concentration region of the low-voltage NMOS transistor is doped with arsenic, while the source/drain high impurity concentration region of the high-voltage NMOS transistor is doped with phosphorus.

This application claims priority under 35 U.S.C. §119 to Japanese PatentApplication No. JP2006-176107 filed Jun. 27, 2006, the entire content ofwhich is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuitdevice which includes an N-channel type low-voltage MOS transistor andan N-channel type high-voltage MOS transistor.

2. Description of the Related Art

In a semiconductor integrated circuit a low-voltage element and ahigh-voltage element are both used, depending on the respective usethereof. For example, a high-voltage element is used only in a sectionwhich directly handles a voltage applied to and sent from thesemiconductor integrated circuit, while a low-voltage element is used ina section which performs internal signal processing. The low-voltageelement occupies a smaller area than the high-voltage element.Accordingly, the use of the high-voltage element only in a section whichdetermines the performance specification of the integrated circuit andis difficult to modify, such as a section relating to voltages exchangedwith outside, and the use of the low-voltage element in a section forperforming the internal processing permit the reduction in the area ofthe semiconductor integrated circuit and the manufacturing cost thereof.

FIG. 2 is a schematic plan view of the above-mentioned low-voltage MOStransistor and the high-voltage MOS transistor formed on the samesubstrate and in the same semiconductor integrated circuit.

The low-voltage N-channel MOS transistor (hereinafter, referred to asNMOS) 101 includes a gate insulating film 8, a gate electrode 9 disposeddirectly above the gate insulating film 8, and a source/drain regionprovided on both ends thereof. The source/drain region includes thefirst N-type high impurity concentration region 2 of low resistance forcontacting metal, and the first N-type low impurity concentration region3 for alleviating electric field intensity.

In this case, the first high concentration N-type region 2 in particularis doped with atoms of, for example, arsenic or antimony, which has asmall diffusion coefficient and whose thermal diffusion is small. Thereason for this is to avoid diffusion of the high impurity concentrationin a lateral direction due to the heat treatment process performedduring the semiconductor processing as much as possible, adverselyresulting in reduction in length of the first N-type low impurityconcentration region 3. The problem can be avoided by securing apredetermined length for the first N-type low impurity concentrationregion 3 if the first N-type low impurity concentration region 3 isdesigned to have an ample length so as to allow for the diffusion, whichleads to, however, an increase in an area to be occupied by the elementto thereby increase cost.

Meanwhile, the high-voltage NMOS 102 includes the gate insulating film8, the gate electrode 9 disposed directly above the gate insulating film8, and a source/drain region provided on both ends thereof. Thesource/drain region includes the second N-type high impurityconcentration region 4 and a second N-type low impurity concentrationregion 5, and the high-voltage NMOS 102 further includes an oxide film10 formed on the second N-type low impurity concentration region 5, theoxide film 10 being thicker than the gate insulating film 8. The thickoxide film 10 has an effect of alleviating the gate-drain electric fieldintensity. The above-mentioned drain structure is adapted to a casewhere the drain needs to be resistant to a voltage of 20 V or more, anda withstanding voltage is adjusted by varying the length and theconcentration of the N-type low impurity concentration region of thedrain. Further, in a case where the gate of the high-voltage NMOS 102 isalso applied with a voltage which is larger than the voltage applied tothe low-voltage NMOS 101, the thickness of the gate insulating film 8may be increased only for the portion corresponding to the high-voltageNMOS 102 according to the voltage.

The second N-type high impurity concentration region 4 of thehigh-voltage NMOS 102 is generally formed through the same process forforming the N-type highly-concentrated impurity region 2 of thelow-voltage NMOS 101 for the purpose of reducing process cost, andarsenic or antimony is used as the impurity to be implanted therein.

Also, the second low impurity concentration region 4 is often used incombination with a channel stop structure provided outside of theelement region, thereby reducing process cost. The second low impurityconcentration region 4 accordingly has an oxide film obtained throughthe LOCOS process disposed thereon, and the concentration of the secondlow impurity concentration region 4 is adjusted to a value that is notinverted due to the wiring. In general, in a case where the high-voltageNMOS is less frequently used in the semiconductor integrated circuit,limitations are imposed on the high-voltage NMOS in terms of structurefor reducing cost as described above, and the element has to be designedunder the limiting conditions.

Further, there may be provided a third N-type low impurity concentrationregion 7 to the depth of several μm on the drain side of thehigh-voltage NMOS 102, in such a manner that the third N-type lowimpurity concentration region 7 covers the entire N-type high impurityconcentration region 4 and a part of the N-type low impurityconcentration region 5. The third N-type low impurity concentrationregion 7 is provided so as to complement a small contact area betweenthe N-type low impurity concentration region 5 and the N-type highimpurity concentration region 4 on the drain side shown in FIG. 3A,which produces an effect of preventing a thermal destruction from beingcaused by a high electric field and a large current to be applied whenthe high-voltage NMOS 102 electrically operates. The thermal destructionphenomenon described above not only results in an instant destructionbut also affects the long-term reliability.

In order to form the N-type low impurity concentration region 7, theregion needs to be doped with an impurity, such as phosphorus, which hasa high diffusion coefficient and is easy to thermally diffuse, and alsoneeds to be subjected to high-heat processing with a temperature of1,000° C. or more in order to attain a certain predetermined diffusiondepth.

The above-mentioned structure of the high-voltage NMOS is disclosed inJP 06-350084 A and in JP 3270405 B.

In the conventional high-voltage NMOS, it is necessary to provide a deepN-type impurity region covering the entire N-type high impurityconcentration region and a part of the N-type low impurity concentrationregion, and the formation of the region additionally involves a heattreatment process, which results in the limitation of the performance ofthe element, and a photolithography process, which leads to an increasein cost. On the other hand, if the deep N-type impurity region is notprovided, there has been a problem that a breakdown withstanding voltageis not sufficiently attained and a long-term reliability is impaired.

SUMMARY OF THE INVENTION

The present invention has been made to solve the above-mentionedproblems, and provides a semiconductor integrated circuit device,including an N-channel type low-voltage MOS transistor and an N-channeltype high-voltage MOS transistor which are formed on a semiconductorsubstrate, the N-channel type low-voltage MOS transistor including: agate insulating film; a gate electrode; and a source/drain region whichis formed of a first N-type high impurity concentration region and afirst N-type low impurity concentration region formed between the gateinsulating film and the first high impurity concentration region, theN-channel type high-voltage MOS transistor including: a gate insulatingfilm; a gate electrode; a second source/drain region which is formed ofa second N-type high impurity concentration region and a second N-typelow impurity concentration region formed between the gate insulatingfilm and the second high impurity concentration region; and aninsulating film formed on the second low impurity concentration region,the insulating film being thicker than the gate insulating film, inwhich the first high impurity concentration region is doped with arsenicand the second high impurity concentration region is doped withphosphorus.

The present invention also provides a semiconductor integrated circuitdevice, including: a first N-channel type low-voltage MOS transistor; anN-channel type high-voltage MOS transistor; and a second N-channel typelow-voltage MOS transistor, which are formed on a semiconductorsubstrate, the first N-channel type low-voltage MOS transistorincluding: a gate insulating film; a gate electrode; and a source/drainregion which is formed of a first N-type high impurity concentrationregion and a first N-type low impurity concentration region formedbetween the gate insulating film and the first high impurityconcentration region, the N-channel type high-voltage MOS transistorincluding: a gate insulating film; a gate electrode; a secondsource/drain region which is formed of a second N-type high impurityconcentration region and a second N-type low impurity concentrationregion formed between the gate insulating film and the second highimpurity concentration region; and an insulating film formed on thesecond low impurity concentration region, the insulating film beingthicker than the gate insulating film, the second N-channel typelow-voltage MOS transistor including: a gate insulating film formed onthe semiconductor substrate; a gate electrode; and a source/drain regionformed of a third high impurity concentration region, in which the firsthigh impurity concentration region is doped with arsenic, and the secondhigh impurity concentration region and the third high impurityconcentration region are each doped with phosphorus.

Also, in the semiconductor integrated circuit device, the first highimpurity concentration region is doped with antimony, and the secondhigh impurity concentration region is doped with phosphorus.

Also, in the semiconductor integrated circuit device, the first highimpurity concentration region is doped with antimony, and the second andthird high impurity concentration regions are each doped withphosphorus.

Further, in the semiconductor integrated circuit device, the second highimpurity concentration region has an impurity concentration of1×10¹⁹/cm³ or more and has a depth of 0.5 μm or more; and the secondN-type low impurity concentration region has an impurity concentrationbetween 1×10¹⁷ to 5×10¹⁷ cm³ and has a depth of 0.3 μm or less.

Further, in the semiconductor integrated circuit device, the first highimpurity concentration region and the second low impurity concentrationregion contact over an area of 0.2 μm or more in thickness.

According to the present invention, it is possible to provide asemiconductor integrated circuit device having a reliable high-voltageNMOS, which is less likely subject to change in element size andperformance deterioration due to an increase in the number of processsteps and high-heat processing while having a high-withstanding voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a schematic cross-sectional view showing a semiconductorintegrated circuit device according to the present invention;

FIG. 2 is a schematic plan view showing a conventional semiconductorintegrated circuit device;

FIG. 3A is a schematic cross-sectional view showing a main part of theconventional semiconductor integrated circuit device;

FIG. 3B is a schematic cross-sectional view showing a main part of thesemiconductor integrated circuit device according to the presentinvention; and

FIG. 4 is a schematic cross-sectional view showing another example ofthe semiconductor integrated circuit device according to the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinbelow, an embodiment of the present invention is described withreference to the accompanying drawings. FIG. 1 is a schematiccross-sectional view of the semiconductor integrated circuit deviceaccording to the present invention, in which a low-voltage NMOS and ahigh-voltage NMOS are integrated on a single semiconductor substrate 1.According to the present invention, the high-voltage NMOS is notprovided with the third N-type low impurity concentration region used inthe conventional example. In stead of providing the third N-type lowimpurity concentration region, the second high impurity concentrationregion 4 of the high-voltage NMOS is formed to be thicker in depth andwider in a lateral direction as compared with the conventionalstructure. With this structure, the second N-type high impurityconcentration region and the second N-type low impurity concentrationregion come into contact with each other over a large area in depth, tothereby prevent a thermal breakdown when applied with a high electricfield and operated with a high current. The thermal breakdown becomesmore noticeable when the above-mentioned contact area reduces to be lessthan 0.2 μm in depth. Accordingly, the present invention adopts thefollowing methods in order to secure the depth of the contact area.

According to a first one of the methods, the second N-type high impurityconcentration region of high-voltage NMOS is doped with phosphorus ofhigh diffusion coefficient, while the first N-type high impurityconcentration region is doped with, as in the conventional case, theatoms of, for example, arsenic or antimony, which has a low diffusioncoefficient.

FIGS. 3A and 3B each are a cross-sectional view of a main part of thesemiconductor integrated circuit device for illustrating the relationbetween the high impurity concentration region and the low impurityconcentration region described above. FIG. 3A shows a junction formed inthe conventional case where the high impurity concentration region dopedwith an impurity of low diffusion coefficient is adopted, whichillustrates that the low impurity concentration region and the highimpurity concentration region contact with each other over a small areain depth. In contrast to this, when the high impurity concentrationregion is doped with atoms of high diffusion coefficient, the highimpurity concentration is more likely to diffuse in a lateral directionas shown in FIG. 3B, to thereby increase the depth of the contact area.

For example, in the high-voltage NMOS structure of FIG. 1, in the casewhere the low-impurity concentration region is doped with phosphorus inconcentration between 1×10¹⁷ and 5×10¹⁷/cm³ and is formed to be 0.3 μmin depth, phosphorous is adopted as the high impurity concentration tobe implanted in the source/drain region of the high-voltage NMOS inconcentration of 1×10¹⁹/cm³ or more, to thereby obtain the high impurityconcentration region of 0.5 μm in depth. In this case, the low impurityconcentration region and the high impurity concentration regiondescribed above can come into contact with each other over an area of0.2 μm in depth, though depending on the heat treatment process to beapplied thereto.

The depth of the contact area may be increased by means of increasingthe diffusion of the low impurity concentration in a lateral direction,instead of increasing the diffusion of the high impurity concentrationin a lateral direction, which is not preferable in terms of reducingcost as described later.

The low impurity concentration region of the high-voltage NMOS of FIG. 1also serves as an element separation region in terms of structure, forthe purpose of reducing the number of process steps. In order to furtherreduce an area necessary for the entire semiconductor integrated circuitso as to contribute to cost reduction, it is effective to set thelow-voltage condition for the element separation region. Thisparticularly produces a larger effect as the low-voltage NMOS accountsfor a larger area in the semiconductor integrated circuit. In this case,the concentration of the low impurity concentration region is inevitablyset to a low value on the low-voltage side. For this reason, it is notpossible to expect the diffusion of the impurity in a lateral directionon the low impurity concentration region side without increasing thenumber of the process steps, and hence the lateral diffusion of the highimpurity concentration region, rather than the low impurityconcentration region, is inevitably desired in the high-voltage NMOS.

In the case of pursuing the reduction of cost as described above, it isgenerally more effective to reduce the low-voltage NMOS in size, whichis mainly used in a logical circuit, so as to produce a larger effect onan area reduction, and it is also preferable that the withstandingvoltage of the low-voltage NMOS be set to be small in itself.Accordingly, it is also necessary, along with the above, to set theconcentration of the low impurity concentration region of the elementseparation region to be low. The depth of the contact area between thelow impurity concentration region and the high impurity concentrationregion can be secured without any significant problem, provided that theconcentration of the low impurity concentration region is equal to orlarger than 1×10¹⁸/cm³. However, the concentration cannot be practicallyset to 1×10¹⁸/cm³ in view of reducing an area, and it is reasonable toprovide a condition with the concentration set between 1×10¹⁷ to5×10¹⁷/cm³. In other words, it is understood that the present inventionis suited for reducing cost as described above and provides a technologycapable of simultaneously integrating the low-voltage NMOS and thehigh-voltage NMOS, to thereby produce a most prominent effect even inthe case of pursuing cost reduction by reducing, for example, the numberof process steps and the area.

In this example, the high impurity concentration region needs to bedoped with the different impurities depending on the withstandingvoltage of the element, which may lead to an increase in process costbecause a photolithography process needs to be additionally involved.Actually, however, it is possible to solve the problem with thestructure shown in FIG. 4.

As shown in FIG. 4, a second low-voltage NMOS 103, which includes thegate insulating film 8, the gate electrode 9, and third N-type highimpurity concentration regions 6, is additionally integrated into thesemiconductor integrated circuit device of FIG. 1. This element is notdirectly used for operating the semiconductor integrated circuit device,but is used for protecting the low-voltage NMOS 101 from anelectrostatic thermal breakdown. Since it has been known that the deeperdiffusion of the source/drain region of the low-voltage NMOS 103 canmore effectively prevent the thermal breakdown, the high impurityconcentration region is generally doped with atoms of, for example,phosphorus, which has a high diffusion coefficient. According to thepresent invention, the source/drain high impurity concentration regionof low-voltage NMOS 103 is formed with the same step of forming the highimpurity concentration region of the high-voltage NMOS 102, to therebyprevent the increase in the number of process steps.

As the second method, in forming the N-type high impurity concentrationregion of the high-voltage NMOS, the impurity is implanted with highenergy so as to be implanted into a portion of the semiconductorsubstrate corresponding to the source/drain region of the high-voltageNMOS and also into another portion of the semiconductor substrate underthe bird's beak formed on the thick oxide film contacting thesource/drain region of the high-voltage NMOS. At this time, it isnecessary to provide a mask to a region other than the source/drainregion and the periphery thereof so as not to be doped with impurities.

Also, at the time of implanting ions as described above, an angle of theimplantation may be adjusted so as to be tilted with respect to thesemiconductor substrate such that the ions are sufficiently implantedinto the semiconductor substrate under the bird's beak, to thereby makethe present invention more effective.

As the third method, the N-type high impurity concentration region ofthe high-voltage NMOS is formed through a thermal diffusion process.This process makes it possible to form the impurity region in highconcentration of 1×10²⁰/cm³ or more, and also to increase the diffusionin a lateral direction in the following heat treatment process. Thelow-voltage NMOS 101 cannot adopt the thermal diffusion process offorming the high impurity concentration region, and therefore, thethermal diffusion process can be only adopted by the present inventionin which the N-type high impurity concentration region of thelow-voltage NMOS and the N-type high impurity concentration region ofthe high-voltage NMOS are separately formed.

With the above-mentioned methods, it is possible to realize a reliablesemiconductor integrated circuit device capable of preventing a thermaldestruction. According to the present invention, the semiconductorintegrated circuit device can be realized with a reduced area necessaryfor the semiconductor integrated circuit through a smaller number ofprocess steps, compared to the conventional device, thereby making itpossible to reduce cost as well as the product TAT.

1. A semiconductor integrated circuit device, comprising: asemiconductor substrate; an N-channel low-voltage MOS transistordisposed on the semiconductor substrate having a first gate insulatingfilm, a first gate electrode, and a first source/drain region formed ofa first N-type high impurity concentration region and a first N-type lowimpurity concentration region for alleviating an electric fieldintensity, wherein the first N-type high impurity concentration regionhas an impurity concentration higher than that of the thirst N-type lowimpurity concentration region; and an N-channel high-voltage MOStransistor disposed on the semiconductor substrate having a second gateinsulating film, a second gate electrode, a second source/drain regionformed of a second N-type high impurity concentration region and asecond N-type low impurity concentration region for alleviating anelectric field intensity, and an insulating film formed on the secondlow impurity concentration region, the insulating film being thickerthan the second gate insulating film, wherein the second N-type highimpurity concentration region has an impurity concentration higher thanthat of the second N-type low impurity concentration region, wherein thefirst N-type high impurity concentration region is doped with a firstimpurity and the second N-type high impurity concentration region isdoped with a second impurity whose diffusion coefficient is larger thanthat of the first impurity wherein in the N-channel high-voltage MOStransistor, the second N-type high impurity concentration region and thesecond N-type low impurity concentration region at least partiallyoverlap with each other at a depth deeper than the thick insulatingfilm.
 2. A semiconductor integrated circuit device according to claim 1,wherein: the first N-type high impurity concentration region is dopedwith arsenic; and the second N-type high impurity concentration regionis doped with phosphorus.
 3. A semiconductor integrated circuit deviceaccording to claim 1, wherein: the first N-type high impurityconcentration region is doped with antimony; and the second N-type highimpurity concentration region is doped with phosphorus.
 4. Asemiconductor integrated circuit device according to claim 1, wherein inthe N-channel high-voltage MOS transistor, the second gate insulatingfilm and the thick insulating film are continuously formed.
 5. Asemiconductor integrated circuit device according to claim 1, wherein inthe N-channel high-voltage MOS transistor, the second gate insulatingfilm and the thick insulating film are continuously formed.
 6. Asemiconductor integrated circuit device according to claim 1, wherein inthe N-channel high-voltage MOS transistor, the second gate electrode atleast partially overlaps the thick insulating film.
 7. A semiconductorintegrated circuit device, comprising: a first N-channel low-voltage MOStransistor; an N-channel high-voltage MOS transistor; and a secondN-channel low-voltage MOS transistor, which are formed on asemiconductor substrate, the first N-channel low-voltage MOS transistorcomprising: a first gate insulating film; a first gate electrode; and afirst source/drain region formed of a first N-type high impurityconcentration region and a first N-type low impurity concentrationregion for alleviating an electric field intensity, wherein the firstN-type high impurity concentration region has an impurity concentrationhigher than that of the thirst N-type low impurity concentration region,the N-channel high-voltage MOS transistor comprising: a second gateinsulating film; a second gate electrode; a second source/drain regionformed of a second N-type high impurity concentration region and asecond N-type low impurity concentration region for alleviating anelectric field intensity, wherein the second N-type high impurityconcentration region has an impurity concentration higher than that ofthe second N-type low impurity concentration region; and an insulatingfilm formed on the second low impurity concentration region, theinsulating film being thicker than the second gate insulating film,wherein the first N-type high impurity concentration region is dopedwith a first impurity and the second N-type high impurity concentrationregion is doped with a second impurity whose diffusion coefficient islarger than that of the first impurity, and the second N-channellow-voltage MOS transistor comprising: a third gate insulating film; athird gate electrode; and a third N-type high impurity concentrationregion, wherein the third N-type high impurity concentration region isdoped with the second impurity wherein in the N-channel high-voltage MOStransistor, the second N-type high impurity concentration region and thesecond N-type low impurity concentration region at least partiallyoverlap with each other at a depth deeper than the thick insulatingfilm.
 8. A semiconductor integrated circuit device according to claim 7,wherein: the first N-type high impurity concentration region is dopedwith arsenic; and the second N-type high impurity concentration regionand the third N-type high impurity concentration region are each dopedwith phosphorus.
 9. A semiconductor integrated circuit device accordingto claim 7, wherein: the first N-type high impurity concentration regionis doped with antimony; and the second N-type high impurityconcentration region and the third N-type high impurity concentrationregion are each doped with phosphorus.
 10. A semiconductor integratedcircuit device according to claim 7, wherein: the second N-type highimpurity concentration region has an impurity concentration of1×10¹⁹/cm³ or more and has a depth of 0.5 μm or more; and the secondN-type low impurity concentration region has an impurity concentrationbetween 1×10¹⁷ to 5×10¹⁷ cm³ and has a depth of 0.3 μm or less.
 11. Asemiconductor integrated circuit device according to claim 7, whereinthe first N-type high impurity concentration region and the secondN-type low impurity concentration region contact over an area at a depthof 0.2 μm or more.
 12. A semiconductor integrated circuit deviceaccording to claim 7, wherein in the N-channel high-voltage MOStransistor, the second gate electrode at least partially overlaps thethick insulating film.